राष्ट्रीय इलेक्ट्रॉनिकी एवं सूचना प्रौद्योगिकी संस्थान ,कालीकट

National Institute of Electronics & Information Technology,Calicut

Ministry of Electronics & Information Technology
Government of India
Course Calendar

VL701 Advanced Diploma - VLSI Physical Design Engineer

Course : Advanced Diploma - VLSI Physical Design Engineer
Code : VL701
Starting Date : 15 May,2019
Last Date To Apply : 30 April,19
Course Coordinator :

Sreejeesh SG  

Email:sreejeesh@nielit.gov.in ,

Phone 0495 -2287266 (ext. 222). Mobile : 9447769756

Course Preamble

VLSI (Very Large Scale Integration) technology has emerged as a very important technology in modern electronics featuring deep sub-micron manufacturing processes, low voltage operations, exploding speeds and smart programmable devices sufficient enough to digest ambient conditions to extremes. The electronics industry worldwide is rapidly approaching another revolutionary leap in the global market scenario. Semiconductor technology has crossed the quarter-micron threshold, making tens of millions of transistors available on a single chip equipped with the powerful arm of VLSI design. This imparts the electronics industry a potential to create designs of incredible densities and lightning speeds while utilizing batt eries to power them. This has had a phenomenal impact on widespread applications rangin g from consumer electronics, communications, and defense to just about everything.

As part of Electronics India program by Govt. of India, most of the electronic products and semiconductor ICs are planning to make in India. This skill development program in VLSI Physical design will help to generate skilled manpower in IC design and manufacturing.

Course Objective

It is proposed to offer Diploma in VLSI Physical Design Engineer to enable new Electronics graduates/post graduates or working engineers in electronic industries to the concepts used in IC Design, which involves processing, Layout, System Design Methods using Cadence tool. The course will benefit VLSI Engineers seeking lateral shift to a back end job. Engineers looking to work for Block level Physical Design Implementation, Place and Route job domains. This will take VLSI Engineers to a new level known as Physical Design Engineer. The Physical Design Engineer is responsible for converting the circuit design to a geometric representation for manufacturing the integrated circuit (IC).

The main objective of the course is to make individuals understand the functional design of IC, converting them into geometric representation to enable Integrated Circuit manufacturing process; verifying and validating the integrated circuit layout.

During course work, each individual will get ample time to practice the theory taught in class in the lab sessions.


Course Outcome

After successful completion of the course individuals will understand the functional design of IC, converting
them into geometric representation to enable Integrated Circuit manufacturing process; verifying and validating the integrated circuit layout. The course will also help to fetch VLSI Physical Design job for job seekers in VLSI area.

Course Structure

VL701 Module Name Duration
Module 1 CMOS Fundamentals, Schematic & Layout  1 Month
Module 2 Digital Physical Design Flow 1 Month
  Project 1 Month


Course Contents

Module 1: CMOS Fundamentals, Schematic & Layout – One Month
CMOS Logic Design: MOS Fundamentals, MOS switches and design, Transmission Gates, CMOS Inverter Characteristics, CMOS Combinational and sequential logic. MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits. Introduction to IC Layout, IC Layout Design Tools

Module 2: Digital Physical Design Flow- One Month 
ASIC Design Concepts, ASIC Design Flow-Frontend and backend, EDA tools for Frontend and backend, Introduction to Verilog HDL, Hardware Modeling Overview
a) Digital ASIC Design Synthesis: Introduction to Digital Synthesis: Synthesize a block-level RTL design to generate a gate-level netlist using Cadence Synthesis Tool.
b) Physical Design Flow Setup and Floorplan List of inputs (libraries, technology files, netlist, timing constraints, and IO placement) to the PD flow, contents of each input, qualifying the received inputs and sanity checks. Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.
c) Power Routing & Placement: Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/Std cell rail. Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, pre-place optimization and in-place optimization, congestion analysis, timing analysis.
d) Timing Analysis & Optimization: Basic timing checks in digital circuits like Setup Time Violations and Hold Time Violations, understanding timing constraints, timing corners, timing report analysis, general optimization techniques, and typical causes for timing violations and strategies for fixing the same.
e) Clock Tree Synthesis (CTS) & Routing: What is Clock Tree Synthesis and its Goals, Types of Clock-tree, CTS Specification, Building clock tree, analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results. Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), and post route optimization.
f) ECO Flow & Sign-off Checks: What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing. Physical Verification (DRC, LVS, ERC), Sign-off Timing analysis.


Project- One Month

One project should be taken up covering RTL to GDS flow. We will adopt the industry standard flow for the implementation. 


Course Fees

Course fee is Rs 35,000/- including GST


M.E/ M.Tech/ B.E/ B.Tech/ M.Sc in Electrical/ Electronics and Communication/ Electronics and Instrumentation/ Com
puter Science and allied branches

Important Dates

First Selection List Publication 1st March 2019
Advance Fee payment Last Date 11th March 2019
2nd Selection List Publication 1st May 2019
Counseling date  13th & 14th May 2019
Class Commencement date 15th May 2019

More Details

For more details like How to Apply, Placement, Hostel, etc please see the Course Calendar

For more Information Contact the course coordinator Mr.Sreejeesh S.G , Email:sreejeesh@nielit.gov.in , Phone 0495 -2287266 (ext. 222). Mobile : 9447769756  or WhatsApp # 9446711666